1. Field of the Invention
The invention relates to fabricating of small geometry semiconductor devices, and more specifically to a method for fabricating semiconductor devices with localized packet implantation.
2. Prior Art
A submicron semiconductor integrated circuit is characterized by small and compact device dimensions. As the size of a semiconductor device is scaled down, the probability of reducing its reliability increases. The main factors that affect the reliability of the small geometry semiconductor device result from the shrinkage of its channel length and width. Therefore, an important issue in submicron device engineering is how to overcome the problems associated with short and narrow channel effects.
The hot carrier effect results from reducing the channel length in a small semiconductor device, which results in oxide charging and other problems that degrade the device. A submicron device with lightly-doped drain (LDD) structure has been used to improve its immunity to the hot carrier effect. However, the LDD structure may cause extension of depletion regions of the source and drain into the substrate region under the gate. This extension of the depletion regions tends to increase the probability of the punchthrough effect limiting the normal operation range of the semiconductor device.
A variety of solutions have been attempted to overcome the hot carrier effect as well as the punchthrough problem. For example, the punchthrough resistance can be improved by adding an ion implantation before or after the LDD formation thus increasing the substrate dopant concentration near the source and drain region. For two regions with opposite conductivity types, the width of their junction depletion region is reduced as the dopant concentrations increase. Therefore the additional implantation of dopant of the substrate conductivity type under the source and drain regions will narrow the width of the depletion regions of the source-substrate and drain-substrate junctions. In order to clarify the structure of the afore-mentioned device and its process flow, an exemplary embodiment is now described with reference to FIG. 1A through FIG. 1C.
The structure is prepared in a silicon substrate of, for example, P-type conductivity. Referring to FIG. 1A, after forming sequentially a silicon dioxide layer 12 and a polysilicon layer overlying silicon substrate 11, a gate electrode 14 of the device is formed by patterning and etching back the polysilicon layer. Therefore, due to the masking effect of gate electrode 14, a P-type implant to silicon substrate 11 forms deep lightly doped regions 17 adjacent to the channel region that is located below gate electrode 14 in substrate 11. P-type regions 17 which are also called pocket regions and have dopant concentrations higher than that in substrate 11.
After the formation of pocket regions 17, lightly doped source and drain regions 15 are formed by an N-type implant into substrate 11, as shown in FIG. 1B. N-type doped regions 15 have a shallow junction depth and have higher dopant concentrations than those of pocket regions 17.
The process is continued by forming spacers 18 around gate electrode 14. Referring to FIG. 1C, another N-type implant is performed to form heavily doped regions 19 in substrate 11. The process may be followed by forming passivation layers above the structure and contact metallization to interconnect the device and other circuitry (not shown in the drawings).
The LDD device fabricated according to the process flow described above has the advantage of suppressing both the hot carrier effect and the punchthrough problem. However, since P-type pocket regions 17 surround the entire N-type source and drain regions 19 in silicon substrate 11, the areas of source-substrate and drain-substrate junctions are so broad that relatively large junction capacitances cannot be eliminated. The larger the junction capacitances, the slower the switching speed of the device, thereby affecting the performance of the circuitry in which this device is utilized.